Memory device for activating one cell by specifying block...

Details Memory device for activating one cell by specifying block... Memory device for activating one cell by specifying block...

2003-01-21

2004-10-19

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S189050, C365S189011

Reexamination Certificate

active

06807124

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to memory devices, and more particularly to a memory device having a plurality of memory cells for storing multi-valued (e.g. binary) information.
2. Description of the Background Art
Memory devices having a plurality of memory cells for storing, e.g., binary information include SRAM (Static Random Access Memory).
FIG. 4
shows an example of structure of an SRAM memory array. As shown in
FIG. 4
, this SRAM memory array includes a plurality of memory cells MC successively arranged in a line. A write bit line WBL, an inverted data write bit line /WBL, and a read bit line RBL are connected to each memory cell MC. In this specification, the symbol “/” denotes logically inverted signal (the same applies hereinafter).
Each memory cell MC is disposed between the write bit line WBL and the inverted data write bit line /WBL and read bit line RBL. As well as these bit lines, read word lines and write word lines are also connected to the memory cells MC (neither is shown in FIG.
4
).
In the SRAM memory array shown in
FIG. 4
, the bit lines for carrying write data or read data and the word lines for selecting memory cells are provided for writing and for reading, respectively. Thus this SRAM memory array is of multiport type which allows write and read operations to be simultaneously performed in the same clock cycle.
Input data DI is provided to the write bit line WBL and the inverted data write bit line /WBL through a write driver
1
for driving both write bit lines. More specifically, the input data DI is given to the write bit line WBL through an inverter I
1
in the write driver
1
. Also, the input data DI is given to the inverted data write bit line /WBL through a series connection of inverters I
2
and I
3
in the write driver
1
.
On the other hand, output data DO is outputted from the read bit line RBL through an inverter I
4
as a read driver for driving data output line.
FIG. 5
shows an example of the structure of the SRAM circuit in the memory cell MC shown in FIG.
4
. As shown in
FIG. 5
, this memory cell MC includes a latch circuit formed of inverters MI
1
and MI
2
each having its input connected to the other's output, an N-channel MOS transistor MN
1
having its source connected to the output of the inverter MI
2
, and an N-channel MOS transistor MN
2
having its source connected to the output of the inverter MI
1
.
The write bit line WBL is connected to the drain of the N-channel MOS transistor MN
1
and the inverted data write bit line /WBL is connected to the drain of the N-channel MOS transistor MN
2
. The write word line WWL is connected to the gates of the N-channel MOS transistors MN
1
and MN
2
in common.
The memory cell MC also includes an inverter MI
3
connected to the source of the N-channel MOS transistor MN
1
, for reading data from the latch circuit. The output of the inverter MI
3
is connected to the source of an N-channel MOS transistor MN
3
. The read bit line RBL is connected to the drain of the N-channel MOS transistor MN
3
and the read word line RWL is connected to its gate.
The memory cell MC is thus formed with a plurality of inverters and transistors.
Now, in the SRAM memory array shown in
FIG. 4
, the N-channel MOS transistor MN
1
in each memory cell MC is connected to the write bit line WBL, the N-channel MOS transistor MN
2
in each memory cell MC is connected to the inverted data write bit line /WBL, and the N-channel MOS transistor MN
3
in each memory cell MC is connected to the read bit line RBL.
In general, parasitic capacitance is present in MOS transistors. Accordingly, when driving at least one of the write bit line WBL, inverted data write bit line /WBL and read bit line RBL that are respectively connected to the drains of the N-channel MOS transistors MN
1
to MN
3
, the bit line is loaded with the drain-substrate capacitances of the MOS transistors in the individual memory cells MC.
Therefore, in order to reduce the load capacitance, all memory cells in the memory device are divided into a plurality of local blocks. In other words, some memory cells are grouped into a block and a plurality of blocks are combined to form a memory device.
FIG. 6
is a diagram showing an example of the structure of an SRAM memory array divided into blocks.
As shown in
FIG. 6
, local blocks LB
0
to LBm (m is a positive number), each including some memory cells MC, are successively arranged in a line. A global write bit line GWBL and a global read bit line GRBL are connected to the local blocks LB
0
to LBm in common. The local blocks LB
0
to LBm are disposed between the global write bit line GWBL and the global read bit line GRBL.
The global write bit line GWBL receives input data DI and the global read bit line GRBL outputs output data DO through an inverter I
4
as a read driver for driving data output line.
In each of the local blocks LB
0
to LBm, a plurality of memory cells MC are successively arranged in a line. In the mth block, a local write bit line LWBLm, a local inverted data write bit line /LWBLm, and a local read bit line LRBLm are connected to each memory cell MC.
In the mth block, the memory cells MC are disposed between the local write bit line LWBLm, and the local inverted data write bit line /LWBLm and local read bit line LRBLm. In addition to these lines, local read word lines and local write word lines (neither is shown in
FIG. 6
) are also connected to the memory cells MC.
In the mth block, the local write bit line LWBLm and the local inverted data write bit line /LWBLm are supplied with the input data DI from the global write bit line GWBL through a local write driver
1
m
for driving both write bit lines. More specifically, the input data DI is given to the local write bit line LWBLm through an inverter I
1
m
in the local write driver
1
m.
Also, the input data DI is given to the local inverted data write bit line /LWBLm through a series connection of inverters I
2
m
and I
3
m
in the local write driver
1
m.
A write selector SWm is provided between the global write bit line GWBL and the write driver
1
m.
The write selector SWm is a switch circuit for providing the input data DI applied to the global write bit line GWBL to a proper block. For example, the write selector SWm is formed as an AND circuit whose one input end is connected to the global write bit line GWBL and whose other input end receives a write block select signal BWm.
On the other hand, the local read bit line LRBLm is connected to the global read bit line GRBL through a read selector SRm. The read selector SRm, too, is a switch circuit, which gives stored data from a proper block to the global read bit line GRBL. For example, the read selector SRm, too, is formed as an AND circuit whose one input end is connected to the local read bit line LRBLm and whose other input end receives a read block select signal BRm.
While the structure of the mth block has been described above, the 0th and other blocks are constructed in the same way.
When the memory cells are divided into blocks as shown above, the drain-substrate capacitances of MOS transistors in the memory cells MC are applied as load only to the local write bit line LWBLm, the local inverted data write bit line /LWBLm, and the local read bit line LRBLm provided in the block to which those memory cells MC belong. Accordingly, when the memory arrays in
FIGS. 4 and 6
have the same number of memory cells MC in total and the individual blocks in
FIG. 6
include the same number of memory cells MC, the local write bit line LWBLm, the local inverted data write bit line /LWBLm, and the local read bit line LRBLm in
FIG. 6
are subjected to a load capacitance that is 1/(m+1) of the load capacitance to the write bit line WBL, the inverted data write bit line/WBL, and the read bit line RBL in FIG.
4
.
Reducing the load capacitance to each bit line suppresses interconnection delay, and therefore dividing the memory cells into blocks as shown above speeds up write and read operations to and from the memory c

Affiliated with

Also associated with

Rating

Memory device for activating one cell by specifying block... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device for activating one cell by specifying block..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device for activating one cell by specifying block... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3284112