Memory device equipped with a RAS circuit

Details Memory device equipped with a RAS circuit Memory device equipped with a RAS circuit

1986-12-23

1988-12-27

Atkinson, Charles E.

Excavating

371 13, G06F 1110

Patent

active

047945974

ABSTRACT:
In a storage unit equipped with a Reliablity, Availability and Serviceability (RAS) circuit, including a memory unit constructed of, e.g., a dynamic random access memory (DRAM) unit, for storing data with an error coding code (ECC), and an ECC unit constructed of e.g., an ECC checking circuit, for correcting a 1-bit error and detecting a 1-bit error, or more than 2-bit error contained in the data read from the memory unit, an ECC diagnostic unit is connected between said memory unit and said ECC unit, and an error made concerning the memory unit and ECC unit is diagnosed by the ECC diagnostic unit by selectively inverting the data read from the memory unit into diagnostic data during the checking operation of the ECC units to diagnose proper operation of the ECC unit and detect erros.

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