Memory device equilibration circuit and method

Details Memory device equilibration circuit and method Memory device equilibration circuit and method

1997-08-06

1998-11-10

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

3652335, 365207, G11C 800, G11C 702

Patent

active

058354409

ABSTRACT:
An equilibration driver circuit provides an equilibration signal on a node in a dynamic random access memory (DRAM). The node is coupled to an equilibration circuit in the DRAM which equalizes voltage levels on complementary pairs of input/output lines in the DRAM in response to the equilibration signal. The equilibration driver circuit comprises an address transition detection circuit having an input terminal adapted to receive a column address signal. The address transition detection circuit is operable to output a pulse signal having a predetermined duration in response to a transition of the column address signal from one logic level to the complementary logic level. A switching circuit has an input terminal receiving the pulse signal and an equilibration terminal coupled to the node. The switching circuit is operable in a first mode to couple the equilibration terminal to a first reference voltage in response to the pulse signal being active. The switching circuit is operable in a second mode to couple the equilibration terminal through a low impedance circuit to a second reference voltage subsequent to the first mode. In a third mode, the switching circuit is operable to couple the equilibration terminal through a high impedance circuit to the second reference voltage subsequent to the second mode.

REFERENCES:
patent: 5732036 (1998-03-01), Meeritt et al.
patent: 5748556 (1998-05-01), Iyengar

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