Memory device control for self-refresh mode

Details Memory device control for self-refresh mode Memory device control for self-refresh mode

2011-01-11

2011-01-11

Nguyen, Viet Q (Department: 2827)

Static information storage and retrieval

Powering

Data preservation

C365S226000, C365S229000

Reexamination Certificate

active

07869300

ABSTRACT:
In memory circuitry, to ensure that a memory device, such as a DDR3 RDIMM, safely operates in self-refresh mode while the memory controller is powered down and off, the memory device's clock enable (CKE) input is connected to both (i) the CKE signal applied by the memory controller and (ii) a termination voltage provided by the power module. To power down the memory controller, the memory controller drives the CKE signal low, then the power module drives the termination voltage low, then the power module powers down the memory controller. To resume normal operations, the power module powers up the memory controller, then the memory controller drives the CKE signal low, then the power module powers up the termination voltage. By holding the termination voltage low, the memory circuitry ensures that the memory device stays in self-refresh mode while the memory device is powered down and off.

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