Memory device command decoding system and memory device and...

Details Memory device command decoding system and memory device and... Memory device command decoding system and memory device and...

2007-09-06

2010-06-01

Phan, Trong (Department: 2827)

Static information storage and retrieval

Powering

C365S227000, C365S228000, C365S229000, C365S233100, C365S233500, C365S222000, C365S230030

Reexamination Certificate

active

07729191

ABSTRACT:
Systems, devices and methods are disclosed. In an embodiment of one such device, an embodiment of a memory device includes a command decoder that is operable to decode received write enable, row address strobe and column address strobe signals to place the memory device in at least one reduced power state despite the absence of either a clock enable signal or a chip select signal. The command decoder performs this function by decoding the write enable, row address strobe and column address strobe signals in combination with at least one address signal received by the memory device. The command decoder can also decode a no operation command, which differs from the at least one reduced power state by only the state of the write enable signal. As a result, when the at least one reduced power state is terminated by a transition of the write enable signal, the memory device automatically transitions to a no operation mode.

REFERENCES:
patent: 6307779 (2001-10-01), Roohparvar
patent: 6512715 (2003-01-01), Okamoto et al.
patent: 6560158 (2003-05-01), Choi et al.
patent: 6667905 (2003-12-01), Dono et al.
patent: 6744687 (2004-06-01), Koo et al.
patent: 7073014 (2006-07-01), Roohparvar
patent: 7212465 (2007-05-01), Kang

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