Memory device column address selection lead layout

Details Memory device column address selection lead layout Memory device column address selection lead layout

1995-06-07

1997-02-11

Zarabian, A.

Static information storage and retrieval

Interconnection arrangements

Magnetic

365 63, G11C 508

Patent

active

056027737

ABSTRACT:
A semiconductor memory device (20) includes N bitlines (31, 32, 33, 34) addressable by a partially decoded column address, wherein N is greater two. A column address selection lead (YSEL) has plural segments, each of which overlays a length of one of the bitlines. Each segment of the column address selection lead overlays no more than approximately 1/N of the length of a bitline. Adjacent column address selection leads are separated by approximately the pitch of N-1 bitlines.

REFERENCES:
patent: 4941031 (1990-07-01), Kumagai et al.
patent: 5014110 (1991-05-01), Satoh

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