Memory device circuit and method for concurrently addressing col

Details Memory device circuit and method for concurrently addressing col Memory device circuit and method for concurrently addressing col

1995-04-11

1997-09-23

Swann, Tod R.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395446, 395477, 365222, 365200, G06F 1200

Patent

active

056713924

ABSTRACT:
A circuit and method for a memory device, such as a synchronous dynamic random access memory (SDRAM) having at least two memory banks. Columns of at least two memory banks are concurrently addressable to permit data to be written to, or read from, the at least two memory banks concurrently. By writing data concurrently to more than one memory bank, testing of the memory of the memory device can be effectuated in a reduced period of time. Data can also be written or read from a single bank in a multi-bank RAM without requiring that a particular bank be specified during a read/write command.

REFERENCES:
patent: 4598388 (1986-07-01), Anderson
patent: 4787067 (1988-11-01), Takemae et al.
patent: 5408677 (1995-04-01), Nogi

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