Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2002-03-14
2004-08-17
Auduong, Gene N. (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S100000, C365S158000
Reexamination Certificate
active
06778421
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention pertains to the field of resistive memory cell arrays. More particularly, this invention relates to a memory array having memory bit pairs sharing a common conductor to increase array density.
A resistive random access memory (RAM) is a cross point type memory array of a planar matrix of spaced memory cells sandwiched between two meshes of conductors running in orthogonal directions above and below the cells. An example is the resistive RAM array
10
shown in FIG.
1
. The row conductors
12
running in one direction are referred to as the word lines, and the column conductors
14
extending in a second direction usually perpendicular to the first direction are referred to as the bit lines. The memory cells
16
are usually arranged in a square or rectangular array so that each memory cell unit
16
is connected with one word line
12
and an intersecting bit line
14
.
In a resistive RAM array, the resistance of each memory cell has more than one state, and the data in the memory cell is a function of the resistive state of the cell. The resistive memory cells may include one or more magnetic layers, a fuse or anti-fuse, or any element that stores or generates information by affecting the magnitude of the nominal resistance of the element. Other types of resistive elements used in a resistive RAM array include poly-silicon resistors as part of a read-only memory, or phase charge material as rewritable memory device.
One type of resistive random access memory is a magnetic random access memory (MRAM), in which each memory cell is formed of a plurality of magnetic layers separated by insulating layers. One magnetic layer is called a pinned layer, in which the magnetic orientation is fixed so as not to rotate in the presence of an applied magnetic field in the range of interest. Another magnetic layer is referred to as a sense layer, in which the magnetic orientation is variable between a state aligned with the state of the pinned layer and a state in misalignment with the state of the pinned layer. An insulating tunnel barrier layer sandwiches between the magnetic pinned layer and the magnetic sense layer. This insulating tunnel barrier layer allows quantum mechanical tunneling to occur between the sense layer and the pinned layer. The tunneling is electron spin dependent, causing the resistance of the memory cell, a function of the relative orientations of the magnetizations of the sense layer and the pinned layer. The variations in the junction resistance for the two states of the sense layer determine the data stored in the memory cell. U.S. Pat. No. 6,169,686, granted to Brug et al. on Jan. 2, 2001 discloses such a magnetic memory cell memory.
Referring to
FIG. 2
, a MRAM memory cell is shown. Memory unit
16
is shown as a three-layer memory cell
20
. In each cell
20
a bit of information is stored according to the orientation of a magnetic sense layer
22
of the cell
20
. Usually, the cell
20
has two stable magnetic states corresponding to the logic states “1” and “0.” The two-way arrow
15
on the sense layer
22
shows this binary-state capability. A pinned layer
24
in the cell
20
is separated from the sense layer by a thin insulator
26
. Pinned layer
24
has a fixed magnetic orientation, such as shown by the one-way arrow
17
on layer
24
. When the magnetic state of the sense layer
22
is oriented in the same direction as the direction of the magnetization of the pinned layer
24
, the cell magnetization is referred to as “parallel.” Similarly, when the magnetic state of the sense layer
22
is oriented in the direction opposite to the direction of the magnetization of the pinned layer
24
, the cell magnetization is referred to as “anti-parallel.” These orientations correspond to a low resistance state and a high resistance state, respectively.
The magnetic state of a selected memory cell
20
may be changed by applying currents to a word line
12
and a bit line
14
crossing the selected memory cell. The currents produce two orthogonal magnetic fields that, when combined, will switch the magnetic orientation of the selected memory cell
20
between the parallel and anti-parallel states. Other unselected memory cells receive only a magnetic field from either the word line or the bit line crossing the unselected memory cells. The single field is not strong enough to change the magnetic orientation of the unselected cells, so they retain their magnetic orientation.
Referring to
FIG. 3
, an MRAM memory array
30
is shown. A sense amplifier
32
is connected to the bit line
34
of a selected memory cell
36
. A voltage V
r
is applied to the word line
38
of the selected memory cell
36
, and sense amplifier
32
applies a voltage to the bit line
34
of cell
36
. The sense amplifier
32
provides an amplified output
39
reflecting the state of the memory cell
36
. The same bit line voltage is applied to all of the bit line
34
, effectively biasing all the cells on unselected rows to zero potential. This action isolates the bit line currents from one another, effectively blocking most of the leakage current that might otherwise flow through secondary paths, possibly causing errors in the sensing function of the selected memory cell.
Several issues relevant to all memory arrays are the need to simplify structures, the desire to increase memory storage density, and the need to reduce conductive lines within the array. The MRAM memory array addresses the first issue very well in that the MRAM bit cell is one of the simplest storage cells currently know. The ability to increase memory storage density has typically been achieved by reducing the size of each cell within the array. The reduction of conductive lines has been limited to how many cells there are arranged in rows and columns.
Accordingly, what is needed is a solution to increasing array density without having to first reduce cell dimensions. Further, what is needed is a solution to reduce conductor paths by sharing common paths with two cell pairs.
SUMMARY OF THE INVENTION
According to the present invention, a magnetic random access memory (MRAM) device having parallel memory planes is disclosed. Each memory plane includes a first magneto-resistive cross point plane of memory cells, a second magneto-resistive cross point plane of memory cells, a plurality of conductive word lines shared between the first and second planes of memory cells, a from plurality of bit lines, each of the first plurality of bit lines coupling one or more cells from the first plane to at least one other memory cell in the first plane, a second plurality of bit lines, each of the second plurality of bit lines coupling one memory cell from the second plane to at least one other memory cell in the second plane and a plurality of unidirectional elements. Further, the one unidirectional element couples a first memory cell from the first plane to a selected word line and a selected bit line in a first conductive direction and a second unidirectional element couples a second cell from the second plane to the selected word line and selected bit line in a second conductive direction. The invention further provides for a unidirectional conductive path to form from a memory cell in the first plane to a memory cell in the second plane sharing the same bit line.
The MRAM device further includes multiple read circuits which are each coupled to one or more groups of memory cells by a respective bit line and operable to sense current flow through a memory cell of the associated groups. The read circuit further comprises a sense amplifier, which may be a current mode sense amplifier.
In an alternative embodiment, a data storage device having parallel memory planes is also disclosed. In the alternative embodiment, first there is included a first resistive cross point plane of memory cells and a second resistive cross point plane of memory cells. Further, a word line plane is shared between the first and second planes of memory cells. A plurality of bit lines is provided where each bi
Auduong Gene N.
Hewlett-Packard Development Company LP.
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