Memory device architectures and operation

Details Memory device architectures and operation Memory device architectures and operation

2006-08-04

2009-06-23

Dinh, Son (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S051000, C365S203000, C365S185180

Reexamination Certificate

active

07551467

ABSTRACT:
Non-volatile memory devices utilizing a modified NAND architecture where ends of the NAND string of memory cells are selectively coupled to different bit lines may facilitate increased memory densities, reduced fabrication steps and faster read operations when compared to traditional NAND memory array architectures. Programming and erasing of the memory cells can be accomplished in the same manner as a traditional NAND memory array. However, reading of the memory cells may be accomplished using charge sharing techniques similar to read operations in a DRAM device or by using one bit line as a ground node for sensing current flow through the strings. The use of bit lines for virtual grounding is further suitable to other array architectures.

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