Computer graphics processing and selective visual display system – Computer graphic processing system – Integrated circuit
Reexamination Certificate
1998-03-19
2001-01-09
Tung, Kee M. (Department: 2776)
Computer graphics processing and selective visual display system
Computer graphic processing system
Integrated circuit
C345S440000, C345S504000, C711S005000
Reexamination Certificate
active
06172687
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device which is suitable for storing and reading out texture data to be mapped on polygons forming an object displayed on a display device and a video image processing apparatus using the same.
2. Description of the Related Art
In recent years, video image processing apparatus has spread for displaying objects positioned in a virtual three-dimensional space by employing computer graphics. Additionally, research and development have been conducted to make the displayed objects close to virtual reality.
In the computer graphics, details on surfaces of a displayed object are called as textures. By reading texture data from a texture map and mapping them on every pixels of polygons forming an appropriate object, tone of color, grain and touch can be formed on the object.
FIGS. 8 and 9
are explanatory diagrams for mapping the texture data.
FIG. 8
illustrates one example of a polygon which is developed on a two-dimensional coordinate plane to be displayed on a display device and stored in a frame buffer.
A polygon P shown in
FIGS. 8 and 9
has three vertexes A, B, and C, each of which has one coordinate of X and Y axes on a texture map storing the texture data to be mapped as vertex data.
For example, a vertex A has coordinate data of (T
x0
, T
y0
) on the texture map, which indicates a position for storing the texture data mapped to the pixel of the vertex A. Vertexes B and C also have coordinate data of (T
x1
, Ty
y1
) and (T
x2
, Ty
y2
) respectively.
In addition, for example, for the pixel at a point D on a ridgeline between the vertexes A and B, coordinate data (T
xi
, T
yi
) on the texture map can be obtained by interpolating the coordinate data (T
x0
, T
y0
) of the vertex A and the coordinate data (T
x1
, Ty
y1
) of the vertex B. For all of the other pixels forming the polygon P, coordinate data on the texture map can be similarly obtained by the interpolation.
On the other hand, on the texture map, each texture of the object is developed like a map and is stored in a memory device, for example, if the object is a rock, texture data for expressing a surface of the rock is developed like a map, and if the object is a tree, texture data for expressing a surface of the tree is developed like a map. In other word, the surface of a rock or tree is not uniform as defined by one data but is continuously varied.
The texture map is obtained by developing the textures, such as the surfaces of a rock or tree, on a plane of X and Y coordinate axes. Therefore, the textures of the surfaces of a rock or a tree cab be obtained by specifying the positions of the X and Y coordinate axes.
FIG. 10
is a diagram showing a relationship between a plane having two axes and one pixel of the polygon on the texture map. In
FIG. 10
, TP means an area of pixels specified by the X and Y coordinate axes on the texture map. Each area of the pixels has texture data. On the other hand, PP means one pixel forming a polygon, and PC means a center of the PP.
A position of the X and Y coordinate axes on the texture map can be specified corresponding to the pixel P. One pixel forming a polygon has dimensions as shown in FIG.
10
. Therefore, one pixel forming a polygon is bestriding over a plurality of adjacent pixels on the texture map. Further, the texture on the surface of an object generally has continuity.
Therefore, the texture data for one pixel forming the polygon is generated by combining the plurality of adjacent pixel data on the texture map, which are overlapped to one pixel forming the polygon.
It is required to read out the texture data for the plurality of pixels from the texture map when generating the texture data for one pixel forming the polygon.
From the view point of video image processing in high speed, it is further preferable to concurrently read out texture data for a plurality of pixels.
However, it was difficult to specify two or more addresses concurrently to a data storage in conventional memory devices. Further, as a plurality of address lines were required for one data storage, it was also difficult to make circuit integration ratio higher in a conventional dual port memory.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a memory device from which a plurality of data can be read out by giving one address.
It is another object of the present invention to provide a memory device from which a plurality of data can be read out without providing additional address lines, thereby not degrading the circuit integration.
It is further object of the present invention to provide a texture memory device which is suitable to read out the texture data in high speed by using computer graphics.
It is furthermore object of the present invention to provide a video image processing apparatus using the memory device from which a plurality of data can be read out by giving one address for storing the texture map.
To attain the above-described problem, a first structure of a memory device according to the present invention includes: m memory array banks, each including row and column address decoders; a first circuit for receiving one address and generating m row addresses and n column addresses by shifting the one address by a predetermined value for each of the m row and n column addresses; and a second circuit for inputting each of the generated m row and n column addresses to the corresponding row and column address decoders of the m memory array banks.
Additionally, in a second structure of the memory device according to the first structure, the one address includes row and column addresses, the first circuit shifts each of the row and column addresses of the one address by a predetermined value to generate the m row and n column addresses, and the second circuit inputs the generated m row addresses to the corresponding row address decoders of the m memory array banks, and inputs the generated n column addresses commonly to the column address decoders corresponding to the m memory array banks.
A third structure of the memory device according to the second structure further includes: a third circuit for combining m×n data read out from the m memory array banks and outputting, at least, one combined data.
In a fourth structure of the memory device according to the third structure, the m and n are 2, and the one address is corresponding to a X and Y coordinate for specifying a position where one texture data is stored on a texture map of a video image processing apparatus.
Further, to attain the above-described problems, a first structure of an video image processing apparatus according to the present invention includes: a memory device storing a texture map to store texture data on a plurality of coordinate positions specified by X and Y axes; and a texture mapping circuit for mapping the texture data read out from the texture map on each of pixels forming each of the plurality of polygons, wherein the memory device includes; two memory array banks respectively including row and column address decoders, a first circuit for receiving one coordinate address specified by X and Y axes on the texture map and generating two addresses by shifting the one coordinate address by one, and a second circuit for inputting each of the generated two addresses to corresponding one of the address decoders of the address decoders of the two memory array banks.
In a second structure of the video image processing apparatus according to the present invention, the row address in each of the two memory array banks is corresponding to either an odd numbered address or an even numbered address of Y coordinate on the texture map.
In a third structure of the video image processing apparatus according to the present invention, the address decoders respectively corresponding to the two memory array banks include row and column address decoders, the one coordinate address includes a Y coordinate address in a Y direction and a X coordinate address in a X direction of the texture map,
Kitamura Kenya
Yagi Hiroshi
Yasui Keisuke
Dickstein , Shapiro, Morin & Oshinsky, LLP
Sega Enterprises Ltd.
Tung Kee M.
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