Static information storage and retrieval – Addressing – Plural blocks or banks
Patent
1997-09-16
1999-06-08
Nelms, David
Static information storage and retrieval
Addressing
Plural blocks or banks
36523002, 36523008, 365205, 36518505, G11C 800
Patent
active
059109270
ABSTRACT:
A memory device having a smaller circuit area but efficiently used is provided. A plurality of main word lines (MWL) extending in a row direction are connected through respective bank latches (BL) to a single global word line (GWL) extending across banks (BANK0, BANK1). Selective activation of an enable signal (BLE) and the global word line (GWL) selects one of the bank latches (BL) to selectively activate an associated main word line (MWL). This state is held by the selected bank latch (BL) after the enable signal (BLE) is inactivated. Then, another enable signal (BLE) is activated to selectively activate another main word line (MWL). Sub-decoders (SD) connected to the main word lines (MWL) are selected independently of each other to independently activate word lines (WL) for each bank (BANK).
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Hamamoto Takeshi
Tsukude Masaki
Mitsubishi Denki & Kabushiki Kaisha
Nelms David
Nguyen Tuan T.
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