Memory device and method using a sense amplifier as a cache

Details Memory device and method using a sense amplifier as a cache Memory device and method using a sense amplifier as a cache

2007-05-08

2007-05-08

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S203000, C365S202000, C365S208000, C365S190000, C365S189050

Reexamination Certificate

active

10967899

ABSTRACT:
A memory device includes a pair of complementary bitlines including a first bitline and a second bitline. A bitline precharge block is coupled between the first bitline and the second bitline. A sense amplifier is coupled to both the first bitline and the second bitline and a sense amplifier precharge block is coupled to the sense amplifier. The sense amplifier precharge block can be activated independently from the bitline precharge block. An isolation block is coupled between the pair of complementary bitlines and the bitline precharge block on one side and the sense amplifier and sense amplifier precharge block on another side.

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patent: 2000-123567 (2000-04-01), None
Gervasi, B.; “Compatible High Availability Cached DDR SDRAM (CHAC DDR),” Sep. 2001.

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