Memory device and method of testing the same

Details Memory device and method of testing the same Memory device and method of testing the same

1975-12-22

1977-10-25

Atkinson, Charles E.

Registers

Systems controlled by data bearing records

Time analysis

324 73R, 340174ED, G11C 2900, G06F 1100

Patent

active

040557545

ABSTRACT:
Integrated circuit memory device and method of testing the same wherein test logic is included in the device for detecting the presence of predetermined patterns applied to the memory cells. The cells are tested in groups to reduce the amount of time required for the test.

REFERENCES:
patent: B483268 (1976-03-01), Chu et al.
patent: 3644899 (1972-02-01), Boisvert, Jr.
patent: 3659088 (1972-04-01), Boisvert, Jr.
patent: 3751649 (1973-08-01), Hart, Jr.
patent: 3815025 (1974-06-01), Jordan
patent: 3873818 (1975-03-01), Barnard
patent: 3961252 (1976-06-01), Eichelberger
Howe, Jr. et al., Troubleshooting Large-Scale Integrated Circuit Units, IBM Technical Disclosure Bulletin, vol. 17, No. 7, Dec. 1974, pp. 1941-1944.
Tsui, Arrangement for Minimized Functional Test of LSI Logic Chips, IBM Technical Disclosure Bulletin, vol. 15, No. 9, Feb. 1973, pp. 2870-2872.
Jordan, Integrated Circuit Testing, IBM Technical Disclosure Bulletin, vol. 13, No. 5, Oct. 1970, pp. 1093-1094.
Balasubramanian, et al., Testing LSI Memory Arrays, IBM Technical Disclosure Bulletin, vol. 17, No. 7 Dec. 1974, pp. 2019-2020.

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