Memory device and method of reading data from a memory device

Details Memory device and method of reading data from a memory device Memory device and method of reading data from a memory device

2005-11-29

2005-11-29

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S187000

Reexamination Certificate

active

06970395

ABSTRACT:
A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

REFERENCES:
patent: 5835443 (1998-11-01), Fujita
patent: 5930197 (1999-07-01), Ishibashi et al.
patent: 6301191 (2001-10-01), Ooishi
patent: 6552955 (2003-04-01), Miki
patent: 6707759 (2004-03-01), Song
patent: 2003/0065900 (2003-04-01), Ishibashi et al.
Copy of International Search Report from corresponding PCT application number PCT/EP2004/010027.

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