Memory device and method of operation

Details Memory device and method of operation Memory device and method of operation

1997-11-25

1999-05-11

Hoang, Huan

Static information storage and retrieval

Analog storage systems

36518503, 36518907, G11C27/00

Patent

active

059034874

ABSTRACT:
An analog memory device includes a memory cell transistor and a memory follower transistor that share a common floating gate. The drain of the memory cell transistor is coupled to a first voltage source. The control gate of the memory cell transistor is coupled to a second voltage source. A programming transistor is coupled between the source of the memory cell transistor and a reference voltage. A comparator receives a first input analog signal to be stored in the memory cell transistor and is coupled to the memory follower transistor to receive the signal held on the floating gate. The output of the comparator is coupled to the control gate of the programming transistor to selectively turn it on to store the analog signal in the memory cell transistor.

REFERENCES:
patent: H1035 (1992-03-01), Haviland et al.
patent: 4890259 (1989-12-01), Simko
patent: 5043940 (1991-08-01), Harari
patent: 5289401 (1994-02-01), Shima
patent: 5566125 (1996-10-01), Fazio et al.
patent: 5629890 (1997-05-01), Eng
patent: 5745414 (1998-04-01), Eng et al.

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