Memory device and method of operating the same with high...

Static information storage and retrieval – Floating gate – Particular biasing

Reexamination Certificate

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C365S185230

Reexamination Certificate

active

07324379

ABSTRACT:
A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.

REFERENCES:
patent: 4733377 (1988-03-01), Aoyama et al.
patent: 5347486 (1994-09-01), Urai
patent: 5638320 (1997-06-01), Wong et al.
patent: 6101118 (2000-08-01), Mulatti et al.
patent: 6606267 (2003-08-01), Wong
patent: 2003/0048689 (2003-03-01), Kim
European Search Report, EP 04 42 5754, dated Feb. 24, 2005.

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