Memory device and method having programmable address...

Static information storage and retrieval – Addressing – Multiplexing

Reexamination Certificate

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C362S189000, C362S230000

Reexamination Certificate

active

07151709

ABSTRACT:
A memory device includes a configurable address register having a first set of input buffers coupled to a first set on address bus terminals and a second set of input buffers coupled to a second set of address bus terminals. In a first addressing configuration, address signals are simultaneously applied to the address bus terminals in the first and second sets, and they are simultaneously stored in respective address registers. In a second addressing configuration, a plurality of sets of address signals are sequentially applied to the address bus terminals in only the first set of address bus terminals. Each set of address signals is then stored in a different address register.

REFERENCES:
patent: 4037215 (1977-07-01), Birney et al.
patent: 4476546 (1984-10-01), Varshney
patent: 5005157 (1991-04-01), Catlin
patent: 5012408 (1991-04-01), Conroy
patent: 5055661 (1991-10-01), Gochi
patent: 5117350 (1992-05-01), Parrish et al.
patent: 5241510 (1993-08-01), Kobayashi et al.
patent: 5261064 (1993-11-01), Wyland
patent: 5293495 (1994-03-01), Nguyen et al.
patent: 5422884 (1995-06-01), Göertz
patent: 5586081 (1996-12-01), Mills et al.
patent: 5684973 (1997-11-01), Sullivan et al.
patent: 5715197 (1998-02-01), Nance et al.
patent: 5748982 (1998-05-01), Smith et al.
patent: 5784636 (1998-07-01), Rupp
patent: 5838307 (1998-11-01), Bouton
patent: 5838932 (1998-11-01), Alzien
patent: 5867430 (1999-02-01), Chen et al.
patent: 5901095 (1999-05-01), Crafts
patent: 5918026 (1999-06-01), Melo et al.
patent: 5954812 (1999-09-01), Shiell et al.
patent: 5982696 (1999-11-01), Rao
patent: 6026465 (2000-02-01), Mills et al.
patent: 6091645 (2000-07-01), Iadanza
patent: 6108251 (2000-08-01), Manning
patent: 6118707 (2000-09-01), Gould et al.
patent: 6150839 (2000-11-01), New et al.
patent: 6163836 (2000-12-01), Dowling
patent: 6178132 (2001-01-01), Chen et al.
patent: 6205497 (2001-03-01), Hamilton et al.
patent: 6211891 (2001-04-01), Wahlig
patent: 6249480 (2001-06-01), Mick
patent: 6326807 (2001-12-01), Veenstra et al.
patent: 6356991 (2002-03-01), Bauman et al.
patent: 6388930 (2002-05-01), Obremski
patent: 6393545 (2002-05-01), Long et al.
patent: 6401139 (2002-06-01), Hamilton et al.
patent: 6425066 (2002-07-01), Moreaux et al.
patent: 6466825 (2002-10-01), Wang et al.
patent: 6484227 (2002-11-01), Mergard et al.
patent: 6505313 (2003-01-01), Phan et al.
patent: 6507898 (2003-01-01), Gibson et al.
patent: 6519690 (2003-02-01), Quimby
patent: 6587394 (2003-07-01), Hogan
patent: 6594735 (2003-07-01), Newell et al.
patent: 6611466 (2003-08-01), Lee et al.
patent: 6684314 (2004-01-01), Manter
patent: 6700821 (2004-03-01), Forbes et al.
patent: 6754779 (2004-06-01), Magro
patent: 6760872 (2004-07-01), Gupta et al.
patent: 6769046 (2004-07-01), Adams et al.
patent: 6823505 (2004-11-01), Dowling
patent: 6938142 (2005-08-01), Pawlowski
patent: 7002868 (2006-02-01), Takahashi

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