Memory device and method having multiple internal data buses...

Static information storage and retrieval – Addressing – Plural blocks or banks

Reexamination Certificate

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C365S230040

Reexamination Certificate

active

11064543

ABSTRACT:
A memory device and method receives write data through a unidirectional downstream bus and outputs read data through a unidirectional upstream bus. The downstream bus is coupled to a pair of internal write data buses, and the upstream bus is coupled to a pair of internal read data buses. A first set of multiplexers selectively couple each of the internal write data buses to any of a plurality of banks of memory cells. Similarly, a second set of multiplexers selectively couple each of the banks of memory cells to any of the internal read data buses. Write data can be coupled to one of the banks concurrently with coupling read data from another of the banks. Also, write data may be concurrently coupled from respective write data buses to two different banks, and read data may be concurrently coupled from two different banks to respective read data buses.

REFERENCES:
patent: 4208715 (1980-06-01), Kumahara et al.
patent: 4503497 (1985-03-01), Krygowski et al.
patent: 4831522 (1989-05-01), Henderson et al.
patent: 4954992 (1990-09-01), Kumanoya et al.
patent: 5003485 (1991-03-01), Francisco
patent: 5202856 (1993-04-01), Glider et al.
patent: 5278957 (1994-01-01), Chan
patent: 5289431 (1994-02-01), Konishi
patent: 5369619 (1994-11-01), Ohba
patent: 5375089 (1994-12-01), Lo
patent: 5384745 (1995-01-01), Konishi et al.
patent: 5517462 (1996-05-01), Iwamoto et al.
patent: 5539691 (1996-07-01), Kozaru et al.
patent: 5597084 (1997-01-01), Parasin
patent: 5619471 (1997-04-01), Nunziata
patent: 5745732 (1998-04-01), Cherukuri et al.
patent: 5847998 (1998-12-01), Van Buskirk
patent: 5856947 (1999-01-01), Fang
patent: 5925118 (1999-07-01), Revilla et al.
patent: 5991223 (1999-11-01), Kozaru et al.
patent: 6038630 (2000-03-01), Foster et al.
patent: RE36655 (2000-04-01), Kozaru et al.
patent: 6061763 (2000-05-01), Rubin et al.
patent: 6081458 (2000-06-01), Lattimore et al.
patent: 6084823 (2000-07-01), Suzuki et al.
patent: 6091662 (2000-07-01), Mochida
patent: 6144604 (2000-11-01), Haller et al.
patent: 6167475 (2000-12-01), Carr
patent: 6195280 (2001-02-01), Lattimore et al.
patent: 6215497 (2001-04-01), Leung
patent: 6219763 (2001-04-01), Lentz et al.
patent: 6269413 (2001-07-01), Sherlock
patent: 6275432 (2001-08-01), Hardee
patent: 6278644 (2001-08-01), Takasugi
patent: 6282588 (2001-08-01), Yamamoto
patent: 6351423 (2002-02-01), Ooishi
patent: 6396749 (2002-05-01), Al-Shamma et al.
patent: 6442646 (2002-08-01), Tsuruta
patent: 6452864 (2002-09-01), Condemi et al.
patent: 6510161 (2003-01-01), Trevitt et al.
patent: 6515927 (2003-02-01), Kitamoto et al.
patent: 6518787 (2003-02-01), Allegrucci et al.
patent: 6587905 (2003-07-01), Correale, Jr. et al.
patent: 6587927 (2003-07-01), Hotta et al.
patent: 6618775 (2003-09-01), Davis
patent: 6636444 (2003-10-01), Uchida et al.
patent: 6662285 (2003-12-01), Douglass et al.
patent: 6704238 (2004-03-01), Izutsu et al.
patent: 6717624 (2004-04-01), Kasai
patent: 6728157 (2004-04-01), Yagishita et al.
patent: 2002/0023191 (2002-02-01), Fudeyasu
Croucher, Phil, “Meaning Behind Ram RAS and CAS”, http://www.kingston.com/tools/umg/umg03.asp, printed Feb. 24, 2006.
Definition of “The Memory Controller”, PC Guide, http://www.pcguide.com/ref/ram/timingController-c.html, printed Aug. 2, 2006.
De Gelas, Johan, “Ace's Guide to Memory Technology”, Ace's Hardware, Jul. 13, 2002, pp. 1-6, http://www.aceshardware.com/read.isp?id=5000172, printed Feb. 24, 2006.
“Dynamic Random Access Memory”, Wikipedia, the free encyclopedia, pp. 1-7, http://en.wikipedia.org/wiki/Dynamic—Random—Access—Memory, printed Feb. 24, 2006.
“How Memory Works”, Kingston Technology, pp. 1-8, http://www.Kingston.com/tools/umg/umg03.asp, printed Feb. 24, 2006.
Kent, Dean, “Ram Guide”, Tom's Hardware, Oct. 24, 1998, p. 1, http://www.tomshardware.com/1998/10/24/ram—guide/page2.html, printed Feb. 24, 2006.

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