Memory device and method having multiple address, data and...

Details Memory device and method having multiple address, data and... Memory device and method having multiple address, data and...

2007-09-10

2009-06-16

Lam, David (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230020, C365S230060, C365S189020, C365S189180

Reexamination Certificate

active

07548483

ABSTRACT:
A dynamic random access memory (“DRAM”) device includes a pair of internal address buses that are selectively coupled to an external address bus by an address multiplexer, and a pair of internal data buses that are selectively coupled to an external data bus by a data multiplexer. The DRAM device also includes a bank multiplexer for each bank of memory cells that selectively couples one of the internal address buses and one of the internal data buses to the respective bank of memory cells. Select signals generated by a command decoder cause the multiplexers to select alternate internal address and data buses responsive to each memory command received by the command decoder.

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