Memory device and method for testing memory devices with...

Details Memory device and method for testing memory devices with... Memory device and method for testing memory devices with...

2006-01-31

2008-03-25

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S201000, C365S200000

Reexamination Certificate

active

07349253

ABSTRACT:
A memory device and method for testing memory devices with repairable redundancy is disclosed. In one embodiment, both the regular memory area and the redundant memory area are subject to the same loads during manufacturing and test processes, and that at least one regular memory cell from a regular memory area and at least one redundant memory cell from a redundant memory area are connected with each other via a coupling circuit. The coupling circuit, in particular during the testing of the operability of the semiconductor memory device or of the memory cells, respectively, determines the state of the regular memory cell and/or the redundant memory cell. Thus, in tested and repaired semiconductor memory devices, so-called redundancy storage space for the repair of defective memory capacity can be provided for repair even in the last memory test step, including full test severity and fulfilling all and any reliability requirements for the repair of high-grade memory devices.

REFERENCES:
patent: 5841709 (1998-11-01), McClure

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