Static information storage and retrieval – Floating gate – Multiple values
Reexamination Certificate
2002-05-09
2003-05-20
Mai, Son (Department: 2818)
Static information storage and retrieval
Floating gate
Multiple values
C365S185210
Reexamination Certificate
active
06567304
ABSTRACT:
BACKGROUND
Memory cells are often characterized as being either write-once or write-many. With a write-once memory cell, an unprogrammed digital state of the memory cell (e.g., logic 1) cannot be restored once it has been switched to a programmed digital state (e.g., logic 0). In contrast, a write-many memory cell (such as a Flash memory cell) allows a user to perform multiple program/erase cycles to the memory cell. While write-many memory cells typically store a single bit of data (representing either a logic 0 or a logic 1), some write-many memory cells can store several bits of data per cell. See, for example, U.S. Pat. No. 6,181,603. Storing multiple bits in a memory cell increases the number of logic states that can be represented by the cell. For example, storing two bits per cell increases the number of logic states that can be stored in a memory cell from two (0 or 1) to four (00, 01, 10, or 11). However, repeated program/erase cycles to the memory cell can make it difficult to reliably read multi-bit data from the memory cell. The high-voltage program/erase disturb of a program/erase cycle can degrade the charge storage device, which decreases the noise margin between logic states stored in the memory cells, making it more difficult or impossible to distinguish one logic level from another.
SUMMARY
The present invention is defined by the following claims, and nothing in this section should be taken as a limitation on those claims.
By way of introduction, the preferred embodiments described below provide a memory device and method for reliably reading multi-bit data from a write-many memory cell. In one preferred embodiment, a non-volatile, write-many memory cell operative to store multiple bits is provided, and the number of program/erase cycles to the write-many memory cell is limited. Limiting the number of program/erase cycles increases the probability that multi-bit data will be correctly read from the memory cell. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
The preferred embodiments will now be described with reference to the attached drawings.
REFERENCES:
patent: 5153462 (1992-10-01), Agrawal et al.
patent: 5264740 (1993-11-01), Wright
patent: 5414829 (1995-05-01), Fandrich et al.
patent: 6034882 (2000-03-01), Johnson et al.
patent: 6134141 (2000-10-01), Wong
patent: 6151246 (2000-11-01), So et al.
patent: 6181603 (2001-01-01), Jyouno et al.
patent: 6219282 (2001-04-01), Tanaka
patent: 6222762 (2001-04-01), Guterman et al.
patent: 6236587 (2001-05-01), Gudesen et al.
patent: 6278633 (2001-08-01), Wong et al.
patent: 6363008 (2002-03-01), Wong
patent: 6376282 (2002-04-01), Corisis
patent: 6376284 (2002-04-01), Gonzalez et al.
“Intel StrataFlash™ Memory Technology Development and Implementation,” Fazio et al., Intel Technology Journal, 13 pages (Q4'1997).
“A 125mm21Gb NAND Flash Memory with 10MB/s Program Throughput,” Nakamura et al., ISSCC 2002/Session 6/SRAM and Non-Volatile Memories/6.4, 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 106-107 (2002).
“On the Go With Sonos,” White et al., Circuits & Devices, pp. 22-31 (Jul. 2000).
“NROM: A Novel Localized Trapping, 2-Bit Nonvolatile Memory Cell,” Eitan et al., IEEE Electron Device Letters, vol. 21, No. 11, pp. 543-545 (Nov. 2000).
“A 512Mb NROM Flash Data Storage Memory with 8MB/s Data Rate,” Maayan et al., ISSCC 2002/Session 6/SRAM and Non-Volatile Memories/6.1, 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 100-101 (2002).
“Ovonic Unified Memory—A High-Performance Nonvolatile Memory Technology for Stand-Alone Memory and Embedded Applications,” Gill et al., ISSCC 2002/Session 12/TD Digital Directions/12.4, 2002 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 202-203 (2002).
“0.13 &mgr;m Metal-Oxide-Nitride-Oxide-Semiconductor Single Transistor Memory Cell with Separated Source Line,” Fujiwara et al., Jpn. J. Appl. Phys. vol. 39, pp. 417-423, Part 1, No. 2A (Feb. 2000).
“Three-Dimensional Memory Array and Method of Fabrication,” U.S. patent application Ser. No. 09/560,626, filing date Apr. 28, 2000, inventor: N. Johan Knall.
“Digital Memory Method and System for Storing Multiple-Bit Digital Data,” U.S. patent application Ser. No. 09/932,701, filing date Aug. 17, 2001, inventors: Michael A. Vyvoda and N. Johan Knall.
“Write-Many Memory Device and Method for Limiting a Number of Writes to the Write-Many Device,” U.S. patent application Ser. No. 09/972,787, filing date Oct. 5, 2001, inventors: David R. Friedman and J. James Tringali.
“64M × 8 Bit NAND Flash Memory,” Samsung Electronics (Oct. 27, 2000).
“How Flash Memory Works,” wysiwyg://8/http://www.howstuffworks.com/flash-memory,htm?printable=1, 5 pages (1998).
“Datalight FlashFX™ 4.06 User's Guide,” p. 11 (Aug. 2000).
“How Does TrueFFS® manage Wear Leveling?,” http://www.m-sys.com/content/information/calcInfo.asp, 2 pages (printed Oct. 5, 2001).
Brinks Hofer Gilson & Lione
Mai Son
Matrix Semiconductor, INC
LandOfFree
Memory device and method for reliably reading multi-bit data... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Memory device and method for reliably reading multi-bit data..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device and method for reliably reading multi-bit data... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3017703