Memory device and method for operating a memory device

Details Memory device and method for operating a memory device Memory device and method for operating a memory device

2006-07-18

2008-12-23

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S230010, C365S230080

Reexamination Certificate

active

07468931

ABSTRACT:
A memory arrangement having a memory area with a plurality of memory locations, to which external addresses can be allocated, and an address decoder which is coupled to the memory area and which includes an address input for applying an external address. The address decoder can be switched so that one of the external addresses of an address range is allocated to each memory location of the memory area, or that one of the external addresses of a sub-address range of the address range is allocated to each memory location only within a part-memory area of the memory area. The address decoder is also arranged for identifying the memory location allocated to the external address applied.

REFERENCES:
patent: 5826108 (1998-10-01), Sonobe
patent: 6240482 (2001-05-01), Gates et al.
patent: 6370073 (2002-04-01), Leung
patent: 0 829 086 (2001-10-01), None

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