Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2001-12-03
2002-07-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080
Reexamination Certificate
active
06414900
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
The present invention relates in general to memory access technology and more particularly to a memory device and method for handling out of range addresses.
BACKGROUND OF THE INVENTION
Many applications require memories which only use a subset of the available address decode combinations. This occurs when the number of possible address combinations is greater than the number of physical locations being addressed within and assigned to a single memory device. A conventional memory device includes an array of memory cells accessed by a row select signal. As long as a valid address is applied, a single row is selected and each bitline for the selected row is driven to a known state by the selected memory cells. However, if an out of range address is applied, none of the rows within the memory device are selected, causing the bitlines to be undriven and float to an unknown logic state. If provisions are not made within the memory device to handle an out of range address, problems such as high current and/or metastability will occur.
Previous efforts to solve the out of range address problem include using a weak feedback latch on each bitline. The weak feedback latch holds the existing logic value on the bitline and keeps it from floating when no row is selected. This approach has the disadvantage of slowing read access times since the feedback latch is always active even when the address is valid and in range. When a valid in range address is applied and a row is selected, the memory cells are forced to overdrive the weak feedback latch whenever the logic state of the bitlines are changed. This performance penalty increases as the supply voltage is lowered. In extreme cases, if the weak feedback latch is not carefully designed, functional failures may occur for those memory cells unable to force the weak feedback latch to transition from one logic level to another.
Another technique for solving the floating bitline problem for out of range addresses includes using a voltage or current differential sensing scheme. However, this scheme has no provision to guarantee the data read from invalid address locations. It is assumed that slight imbalances in the feedback of the sense amplifier used in such a scheme will eventually cause the bitline to resolve to either one logic level or the other after some period of time. While it is true that the sense amplifier will eventually resolve to a full logic state, excess power is consumed every time an out of range address condition occurs. The excess power consumption results from the metastable condition created when the sense amplifier is enabled with no differential voltage present on the bitlines.
Thus, conventional approaches to solving the floating bitline problem add to the access time when reading from and writing to a memory device and add to the power consumption of the memory device. Therefore, it is desirable to prevent a bitline from floating upon the occurrence of an out of range address that substantially improves the access time and power consumption of the memory device.
SUMMARY OF THE INVENTION
From the foregoing, it mat be appreciated by those skilled in the art that a need has arisen for a memory device that can effectively handle out of range addresses. In accordance with the present invention, a memory device and method are provided that substantially eliminate or greatly reduce disadvantages and problems of conventional memory devices.
According to an embodiment of the present invention, there is provided a memory device for handling out of range addresses that includes a memory array having a plurality of storage units arranged in a plurality of rows and a bitline driver also having a plurality of storage units. A row decoder receives address information and determines which one of the plurality of rows of the memory array is to be accessed. A row selector selects one of the plurality of rows determined by the row decoder in order to output values stored in its associated storage units. An out of range decoder receives address information and determines that none of the plurality of rows of the memory array is to be accessed for the received address information. An out of range selector selects the storage units of the bitline driver in response to the out of range decoder determining that the received address information does not access any of the plurality of rows of the memory array in order to provide an output from the memory device.
The present invention provides various technical advantages over conventional memory devices. For example, one technical advantage is to eliminate the use of feedback latches and sense amplifiers to drive the bitlines of a memory during the occurrence of an out of range address. Another technical advantage is to detect for an out of range address. Yet another technical advantage is to drive the bitlines of the memory device upon the occurrence of an out of range address. Further technical advantages include predictable data output when accessing out of range addresses, faster access times, lower voltage functionality, and no floating bitlines. Other technical advantages may be readily apparent to those skilled in the art from the following figures, description, and claims.
REFERENCES:
patent: 5784331 (1998-07-01), Lysinger
patent: 5933386 (1999-08-01), Walker et al.
Jamison George B.
Spriggs Stephen W.
Brady III W. James
Hoang Huan
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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