Memory device and method for burn-in test

Details Memory device and method for burn-in test Memory device and method for burn-in test

2006-08-29

2006-08-29

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

C365S185220, C365S201000

Reexamination Certificate

active

07099224

ABSTRACT:
A memory device and a method for burn-in test. The memory device has a plurality of sub-array word line leak-current limited units and a plurality of single word line leak-current limited units. They are used to limit the current in each word line to a predetermined word line current value. In burn-in test mode, the output of a word line driver is kept in a high impedance state. The bit line stress voltage is applied to the row of memory cells through a normal read-write path. A voltage generator for generating a substantially stable voltage is also provided. In burn-in test mode, the even word lines and the odd word lines are grouped separately and the word line stress voltage is applied to the even word lines and to the odd word lines alternately.

REFERENCES:
patent: 6169694 (2001-01-01), Nam et al.
patent: 6266286 (2001-07-01), Cho et al.

Affiliated with

Also associated with

Rating

Memory device and method for burn-in test does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device and method for burn-in test, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device and method for burn-in test will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3614666