Memory device and method

Details Memory device and method Memory device and method

2008-06-06

2010-11-23

Mulpuri, Savitri (Department: 2812)

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

With electrical circuit layout

C438S006000, C438S128000, C257SE21613, C257SE21657, C365S185170, C365S185210, C365S185330

Reexamination Certificate

active

07838342

ABSTRACT:
During first portion of a first read cycle determining that a first input of a sense amplifier is to receive information based upon a state of a storage cell during a first portion of a read cycle, and determining that a conductance at the first input is substantially equal to a conductance at a second input of the sense amplifier during the first portion. A plurality of NAND string modules are connected to a global bit line of a memory device that includes a memory column where a plurality of NAND strings and a buffer are formed.

REFERENCES:
patent: 4523110 (1985-06-01), Johnson
patent: 4549299 (1985-10-01), Palma et al.
patent: 4567445 (1986-01-01), Berg
patent: 5416918 (1995-05-01), Gleason et al.
patent: 5590074 (1996-12-01), Akaogi et al.
patent: 5672989 (1997-09-01), Jang et al.
patent: 5717640 (1998-02-01), Hashimoto
patent: 5732018 (1998-03-01), Choi et al.
patent: 5768191 (1998-06-01), Choi et al.
patent: 5805498 (1998-09-01), Lee et al.
patent: 5946238 (1999-08-01), Campardo et al.
patent: 6154864 (2000-11-01), Merritt
patent: 6195279 (2001-02-01), Townley et al.
patent: 6344760 (2002-02-01), Pyo
patent: 6449202 (2002-09-01), Akatsu et al.
patent: 6914812 (2005-07-01), Owen
patent: 2002/0186591 (2002-12-01), Lee et al.
patent: 2004/0145024 (2004-07-01), Chen et al.
patent: 2005/0078519 (2005-04-01), Shiga
patent: 2006/0034122 (2006-02-01), Betser et al.
patent: 2007/0147113 (2007-06-01), Mokhlesi et al.
U.S. Appl. No. 12/134,905 Office Action mailed Oct. 6, 2009, 5 pages.
U.S. Appl. No. 12/134,898, filed Jun. 6, 2008 entitled “Memory Device and Method”.
U.S. Appl. No. 11/134,905, filed Jun. 6, 2008, entitled “Memory Device and Method”.
Jung, et al., “A 3.3-V Single Power Supply 16-Mb Nonvolatile Virtual DRAM Using a NAND Flash Memory Technology,” IEEE Journal of Solid State Circuits, vol. 32, No. 11, Nov. 1997, pp. 1748-1757.
U.S. Appl. No. 12/134,898, Office Action mailed Jan. 20, 2010, 10 pages.
U.S. Appl. No. 12/134,898, Final Office Action mailed Jun. 29, 2010, 14 pages.
Notice of Allowance mailed Sep. 9, 2010 for U.S. Appl. No. 12/134,898, 14 pages.
Non-Final Office Action mailed Aug. 25, 2010 for U.S. Appl. No. 12/134,905, 9 pages.

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