Memory device and memory control circuit

Details Memory device and memory control circuit Memory device and memory control circuit

1996-10-01

1998-06-09

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

365194, 3651895, G11C 800, G11C 700

Patent

active

057645914

ABSTRACT:
A memory device having a memory element including a plurality of memory cells each designated by a row address signal and a column address signal, and a circuit for detecting a transition between the row address signal and the column address signal to thereby effect an equalize operation on the memory element. The supply of a row/column address signal including the row address signal and the column address signal to the memory element is cut off during a logical indeterminate period at the time of the transition. The row/column address signal immediately before its cutoff is held and the held signal is supplied to the memory element during the logical indeterminate period. Thus, a high-speed operation can be done by the equalize operation and the cutoff can provide the prevention of occurrence of a malfunction due to noise such as a glitch or the like.

REFERENCES:
patent: 5602795 (1997-02-01), Sandhu
patent: 5651126 (1997-07-01), Bailey et al.

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