Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Rendering selected devices operable or inoperable
Reexamination Certificate
2005-03-08
2005-03-08
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Rendering selected devices operable or inoperable
C438S778000, C438S599000
Reexamination Certificate
active
06864123
ABSTRACT:
A technique for manufacturing memory devices which can easily manufacture ROM semiconductors having various write patterns at lower cost in a short period of time is disclosed. Since a simple matrix structure in which each memory cell is formed at a cross-point of an upper and a lower linear electrode is employed, and an insulating material is selectively ejected to surfaces of electrodes at predetermined memory cell positions by using an inkjet head, the surfaces of the electrode at the predetermined memory cell positions are covered with the insulating material. A state is stored in accordance with the presence or the absence of the covering insulating film on the surface of the electrode at each memory cell position.
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Fourson George
Oliff & Berridg,e PLC
Seiko Epson Corporation
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