Memory device address decoding

Details Memory device address decoding Memory device address decoding

2000-08-31

2001-10-16

Fears, Terrell W. (Department: 2824)

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

C365S189050, C365S230080

Reexamination Certificate

active

06304510

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The present invention relates generally to memory devices and in particular the present invention relates to efficient timing of address decoding in memory devices.
BACKGROUND OF THE INVENTION
Synchronous dynamic random access memory (SDRAM) devices operate by accessing memory cells in synchronization with a clock signal. The access speed of the device is dependant upon an address decoding time, data sensing timing, and data output driving time. An increase in the clock frequency will increase the access speed requirements. A problem is experienced when the clock frequency exceeds the process speed of internal memory cell access operations. For example, to access a column of a memory array, an address signal is decoded and column select circuitry is activated. The clock speed either needs to be decreased or a more efficient use of the time between clock cycles is needed.
A problem with SDRAM is the volatile nature of the memory cells. Non-volatile memory devices such as flash memory are available, but do not operate in a synchronous manner. One problem with operating a non-volatile memory in a synchronous manner, such as an SDRAM, is the ability to efficiently use available clock cycle times to perform address decode and memory array access operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an efficient address decoding system for a memory device. Further, there is a need in the art for a non-volatile memory that has a more efficient address decoding system.
SUMMARY OF THE INVENTION
The above-mentioned problems with memory addressing and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a memory device comprises an address input connection to receive memory array address signals, an address input buffer coupled to the address input connection, and a first latch circuit coupled to the address input buffer to latch the memory array address signals. The memory further comprises decode circuitry to decode the memory array address signals, and a second latch circuit coupled to an input of the decode circuitry to latch the memory array address signals coincident with the first latch circuit.
A memory device in another embodiment comprises address input connection to receive memory array address signals, an address input buffer coupled to the address input connection, a first latch circuit coupled to the address input buffer to latch the memory array address signals, and an internal address counter circuit to advance the received memory array address signals. A multiplex circuit is provided that has a first input coupled to the first latch circuit and a second input coupled to the internal address counter circuit. The multiplex circuit includes an output that is coupled to a second latch circuit to latch the memory array address signals coincident with the first latch circuit. The memory includes decode circuitry to decode the memory array address signals coupled to the multiplex circuit.
In another embodiment, a synchronous non-volatile memory device comprises an array of non-volatile memory cells arranged in addressable rows and columns, address input connections to receive memory array address signals, and an address input buffer coupled to the address input connections. A first latch circuit is coupled to the address input buffer to latch the memory array address signals during a first clock period. The memory further comprises an internal address counter circuit to advance the received memory array address signals, and a multiplex circuit having a first input coupled to the first latch circuit and a second input coupled to the internal address counter circuit. The multiplex circuit includes an output that is coupled to a second latch circuit to latch the memory array address signals during the first clock cycle. A decode circuitry, to decode the memory array address signals, is coupled to the multiplex circuit.
In yet another embodiment, a method of operating a memory device comprises receiving externally provided address signals, latching the address signals in a first latch circuit prior to a first clock signal active transition, and latching the address signals in a second latch circuit prior to the first clock signal active transition. The first latch circuit is coupled to an input buffer circuit and the second latch circuit is coupled to an address decoder circuit.


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