Memory device

Details Memory device Memory device

2002-10-07

2004-11-16

Elms, Richard (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189011, C365S191000, C365S194000

Reexamination Certificate

active

06819625

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention refers to a memory device, and particularly to a memory device with a data stub bus topology (DQ stub bus topology).
2. Description of the Related Art
In the following, an example for a prior art memory device with a data stub bus topology will be discussed in more detail with reference to FIG.
1
. In the example shown in
FIG. 1
, the memory device comprises a first memory module
100
and a second memory module
102
. The illustrated memory modules
100
and
102
are, for example, DIMMs (DIMM=
D
ual
I
nline
M
emory
M
odule). The two memory elements
104
and
106
, for example DRAMs, are shown exemplarily in
FIG. 1
, arranged in the first memory module
100
. Further, as example, two memory elements
108
and
110
, such as also DRAMs of the second memory module
102
are shown.
The memory device further comprises a controller
112
, by which reading in/reading out of data to/from the memory elements
104
to
110
of the memory modules
100
and
102
is controlled. Therefore, the controller
112
is coupled to further elements of a data processing means via connections, not shown in
FIG. 1
, initiating access to one or several of the memory elements. Further, the memory device comprises means
114
for providing a read clock (read clock generator), connected to further elements, such as a phase lock loop providing the requested signals for generating and providing the read clock, respectively, via a connection, also not shown in FIG.
1
.
The memory modules
100
,
102
, the controller
112
and means
114
are connected via bus systems for data exchange and data transfer, respectively, that will be described in more detail below.
In the illustrated embodiment, the memory device according to
FIG. 1
comprises a data bus (DQ) comprising a first sub-data bus
116
and a second sub-data bus
118
. The first sub-data bus
116
comprises a first portion
116
a
extending from the controller
112
to a branch
116
b
. A second portion
116
c
of the first sub-data bus
116
extends from the branch
116
b
to the memory element
104
in the first memory module
100
. A third portion
116
d
of the first sub-data bus
116
extends from the branch
116
b
to the first memory element
108
in the second memory module
102
. The second sub-data bus
118
comprises a first portion
118
a
extending from the controller
112
to a branch
118
b
. A second portion
118
c
of the first sub-data bus
118
extends from the branch
118
b
to the second memory element
106
in the first memory module
100
. A third portion
118
d
of the second sub-data bus
118
extends from the branch
118
b
to the second memory element
110
in the second memory module
102
.
Further, a read clock bus is provided, comprising a first sub-read clock bus
120
and a second sub-read clock bus
122
. As can be seen in
FIG. 1
, a first portion
120
a
of the first sub-read clock bus
120
extends from the controller
112
to a first branch
120
b
. A second portion
120
c
of the first sub-read clock bus
120
extends from the branch
120
b
to the first memory element
104
in the first memory module
100
. A third portion
120
d
of the first sub-read clock bus
120
extends from the first branch
120
b
to a second branch
120
e
. A fourth portion
120
f
of the first sub-read clock bus
120
extends from the second branch
120
e
to the first memory element
106
in the second memory module
102
. A fifth portion
120
g
of the first sub-read clock bus
120
extends from the second branch
120
e
to the read clock generator
114
. A first portion
122
a
of the second sub-read clock bus
122
extends from the controller
112
to a first branch
122
b
. A second portion
122
c
of the second sub-read clock bus
122
extends from the branch
122
b
to the second memory element
106
in the first memory module
100
. A third portion
122
d
of the second sub-read clock bus
122
extends from the first branch
122
b
to a second branch
122
e
. A fourth portion
122
f
of the second sub-read clock bus
122
extends from the second branch
122
e
to the second memory element
110
in the second memory module
102
. A fifth portion
122
g
of the second sub-read clock bus
122
extends from the second branch
122
e
to the read clock generator
114
.
The mode of operation of the memory device illustrated in
FIG. 1
is such that when reading data from the memory elements of the memory modules, the data will be provided on the respective data bus
116
or
118
, and according to the read clock provided by the read clock generator
114
on the read clock bus
120
or
122
, provided to the controller
112
.
When writing data to the memory modules
100
or
102
, the data to be written will be placed on the data buses
116
and
118
, respectively, by the controller
112
, and at the same time a write clock bus, not shown in
FIG. 1
, is provided, extending from the controller
112
to each of the memory elements
104
to
110
. Concurrently with providing data to the data bus the respective clock signals will be provided to the write bus, so that when writing data to the memory elements
104
to
110
the data on the data bus as well as the clock signal on the write clock bus are applied substantially concurrently to a chosen memory element, i.e. between the data to be written on the data bus
116
and
118
, respectively, and a write clock, no time delay can be recognized at the memory element to be written to.
The situation is different when reading data, and here, problems occur with the memory system described in
FIG. 1
, that are only very difficult to solve. As has been mentioned above, the read clock serves to read the data output by the memory elements into the controller. A problem is the implementation of the read clock bus in the DQ stub bus topology illustrated in
FIG. 1
, since here, as can easily be seen, a topology asymmetry between the topology of the data bus (DQ-bus) and the topology of the read clock buses exists, which leads to a delay between the read data and the read clock at the controller. The mentioned asymmetry is that the data bus and the read clock bus extend with different lengths through the memory system. While the buses along the portions
116
a
to
116
d
and
120
a
to
120
f
and along the portions
118
a
to
118
d
and
122
a
to
122
f
, respectively, are parallel, the read clock bus additionally comprises portions
120
g
and
122
g
, respectively, due to the necessary connection to the read clock generator
114
, so that a clock signal output by the read clock generator
114
first has to pass the portions
120
g
and
124
g
, respectively, and experiences here a respective run time delay, before it enters with exactly that delay into the area of the read clock bus running in parallel to the data bus.
With reference to
FIGS. 2 and 3
, the problems underlying the prior art systems will be discussed in more detail. In
FIG. 2
, a portion of the memory system of
FIG. 1
is illustrated, and here, as an example, the first memory element
108
of the second memory module
102
, as well as a portion of the data bus
116
and a portion of the read clock bus
120
. As is indicated by the arrows, the read clock (read_clock) is applied to the bus
120
, while data (data) are read out on the bus
116
from the memory element
108
, such as a DRAM.
The data read out from the memory element
108
will be sent in-phase to the read clock received at the memory element
108
. If data are to be read from a memory element
108
, the controller
112
initiates a respective instruction and data will be read out from the memory element according to the read clock. As can be seen from
FIG. 2
, data propagate from the memory element
108
via the portion
116
d
of the data bus
116
to the controller
112
. Coming from the read clock generator
114
, the read clock propagates via the portion
120
g
of the read clock bus
120
to the memory element
108
and concurrently to the portion
120
h
(see F

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