Memory device

Details Memory device Memory device

1989-02-06

1991-10-08

Smith, Jerry

Excavating

371 211, G06F 1100

Patent

active

050560891

ABSTRACT:
A memory system storing data detects and corrects an error in the stored data. The memory device includes a coding circuit for generating a systematic code including a data word and an error checking and correcting (ECC) code when the data word is supplied from a data bus during data writing, a memory cell array for storing the systematic code, and a sense amplifier for reading the systematic code from the memory cell. An error checking and correcting system generates a syndrome from the systematic code, decodes the syndrome to determine whether an error exists, identifies a bit position at which an error has occurred, and corrects the error contained in the data word by inverting a bit of the data word in the position at which the error has occured. The system includes a multiplexer for outputting the corrected data word to the data bus and a code reading circuit, for example, an ECC code register, for reading the ECC code generated by the coding circuit directly into the data bus. With this arrangement, it is possible to immediately and independently check the function of the coding circuit without influence from the memory cell array.

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Bottorff et al., Self-Testing Scheme Using Shift Register Latches, IBM Technical Disclosure Bulletin, vol. 25 No. 10 Mar. 1983, pp. 4958-4960.
Bhavsar et al., Self-Testing By Polynomial Division 1981 International IEEE, pp. 208-316.

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