Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2001-10-24
2003-05-20
Phan, Trong (Department: 2818)
Static information storage and retrieval
Read only systems
Semiconductive
C365S175000
Reexamination Certificate
active
06567296
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory device.
2. Discussion of the Related Art
Different types of memory devices have been proposed in the last years. For instance, a phase-change E
2
PROM (Electrical Erasable Programmable Read-Only Memory) is a non-volatile memory employing memory cells made of a material that can be electrically switched between a generally amorphous phase and a generally crystalline phase. The phase-change material exhibits different electrical characteristics depending on its state, each one representing a corresponding logic value of the memory cell. An example of a phase-change E
2
PROM is described in U.S. Pat. No. 5,166,758.
Each memory cell is individually selected through a corresponding access element, typically consisting of a MOS transistor or a diode. The solution employing the access diodes is more compact, and requires a smaller space in a chip of semiconductor material wherein the access diodes are integrated.
In order to attain a still higher density of the memory device, it would be desirable to arrange several access diodes in a common insulated region of the chip, which defines a common cathode thereof, multiple regions of the opposite type of conductivity extend into the common region and define corresponding anodes of the access diodes.
Unfortunately, the structure described above creates a stray bipolar transistor between each couple of adjacent access diodes. These stray transistors have a detrimental impact on the memory device performance. Particularly, each time the access diode of a selected memory cell is forward biased, a current flows through the access diode from the corresponding anode to the common cathode. However, part of this current is collected by the (unselected) memory cells associated with the same common region through the corresponding stray transistors. This leakage may cause a malfunctioning of the memory device (for example, with the selected memory cell that is not written or read correctly).
Moreover, the current collected by the other memory cells associated with the common region may bring about an undesired change of phase of the corresponding material, with a loss of data stored in the memory device.
A possible solution could be that of providing guard bars with a high level of impurity between the access diodes. In this way, the gain of the stray transistors (and then the amount of current injected into the unselected memory cells) is greatly reduced.
A different solution could be that of arranging a contact region with a high level of impurity between each couple of adjacent access diodes formed in the same common region. These contact regions (defining a common cathode terminal of the access diodes of each common region) directly collect the current from the common region, thereby greatly reducing the amount of current injected into the unselected memory cells.
However, the solutions proposed above are not completely satisfactory. Particularly, these solutions result in a larger area of each memory cell, and then in a reduced density of the memory device. Moreover, they require additional operations, which increase the complexity of the process for producing the memory device (and then its cost).
SUMMARY OF THE INVENTION
It is an object of the present invention to overcome the above-mentioned drawbacks. In order to achieve this object, a memory device as set out in the first claim is proposed.
Briefly, the present invention provides a memory device including a plurality of memory cells, a plurality of insulated first regions of a first type of conductivity formed in a chip of semiconductor material, at least one second region of a second type of conductivity formed in each first region, a junction between each second region and the corresponding first region defining a unidirectional conduction access element for selecting a corresponding memory cell connected to the second region when forward biased, and at least one contact for contacting each first region. A plurality of access elements are formed in each first region, the access elements being grouped into at least one sub-set consisting of a plurality of adjacent access elements without interposition of any contact; the memory device further includes means for forward biasing the access elements of each sub-set simultaneously.
Moreover, the present invention also provides a corresponding method of operating a memory device.
Further features and the advantages of the solution according to the present invention will be made clear by the following description of a preferred embodiment thereof, given purely by way of a non-restrictive indication, with reference to the attached figures, in which:
REFERENCES:
patent: 4795657 (1989-01-01), Formigoni et al.
patent: 5166758 (1992-11-01), Ovshinsky et al.
patent: 5635745 (1997-06-01), Hoeld
patent: 6404665 (2002-06-01), Lowrey et al.
Bez Roberto
Casagrande Giulio
Czubatyj Wolodymyr
Hudgens Stephen
Lowrey Tyler
Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Jorgenson Lisa K.
Phan Trong
STMicroelectronics S.r.l.
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