Memory device

Details Memory device Memory device

1989-11-01

1991-07-30

Wojciechowicz, Edward J.

Static information storage and retrieval

Magnetic bubbles

Guide structure

357 2311, 357 41, 357 42, 357 46, 357 59, 365185, H01L 2978

Patent

active

050363786

ABSTRACT:
A compact, high speed EEPROM is disclosed. The design features mirror-image pairs of cells with a common junction buried under a thick oxide. The oxide also supports a portion of the control and floating gates. A single erase gate, also above the oxide, is capable of erasing two rows of cells at once. Each cell also has a second junction which contacts the semiconductor substrate surface. The second junction has a conductive landing pad which facilitates small cell size.

REFERENCES:
patent: 4361847 (1982-11-01), Harari
patent: 4409723 (1983-10-01), Harari
patent: 4490900 (1985-01-01), Te-Long Chiu
patent: 4558344 (1985-12-01), Perlegos
patent: 4701776 (1987-10-01), Perlegos et al.
patent: 4750024 (1988-06-01), Schreck
patent: 4844776 (1989-07-01), Lee et al.
patent: 4853895 (1989-09-01), Mitchell et al.
patent: 4855800 (1989-08-01), Esquivel et al.

Affiliated with

Also associated with

Rating

Memory device does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory device will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1545845