Memory device

Excavating

Patent

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Details

324 73R, G01R 3128

Patent

active

046285105

ABSTRACT:
A memory device in accordance with the invention has an array of memory cells including a plurality of main memory cells which are adapted to be utilized by a user for storing information and a plurality of checking memory cells which store data placed therein at the time of manufacturing of the array which is read out to check a performance characteristic of the array of memory cells prior to the storing of data in the main memory cells. Addressing means are associated with the array of memory cells for permitting selective addressing of either the main memory cells or the checking memory cells within the array by the application of selected first or second signal levels to addressing lines coupled to the array. An output circuit is coupled to the array of memory cells for outputting data from within selected cells within the array in cooperation with the addressing circuit. An inhibiting circuit is provided for inhibiting the outputting of data from the output circuit in response to the application of a control signal of a first predetermined magnitude.

REFERENCES:
patent: 3805152 (1974-04-01), Ebersman et al.
patent: 4301535 (1981-11-01), McKenny et al.
patent: 4320507 (1982-03-01), Fukushima et al.
patent: 4459694 (1984-07-01), Ueno et al.

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