Memory device

Details Memory device Memory device

1992-03-26

1993-09-21

LaRoche, Eugene R.

Static information storage and retrieval

Addressing

36523005, 36523008, 36518904, 36518905, 365233, G11C 800, G11C 700

Patent

active

052474852

ABSTRACT:
In a memory device according to the present invention, an address for writing input data into a memory (306) is designated by a first address counter (303) which operates in response to a first clock, an address for reading written data from the memory (306) is designated by a second address counter which operates in response to a second clock, and a phase difference between the outputs of the individual address counter means (303, 313) is detected by a phase comparing section (307). A timing generating section (114-116) delays a signal acquired from the first or second clock to generate three or more timings, a time difference between any two of the timings being a any non-integer multiple of the first or second clock cycle. Further, a phase comparison discriminating section (120-122, 126) latches the output of the phase comparing section (307) at three or more timings, and outputs a signal for controlling a second address counter section (313) by majority decision on the latching result.

REFERENCES:
patent: 4682048 (1987-07-01), Ishimoto
patent: 4688094 (1987-08-01), Tanabe et al.
patent: 4734880 (1988-03-01), Collins
patent: 4829475 (1989-05-01), Ward et al.
patent: 4891788 (1990-01-01), Kreifels

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