1986-04-10
1987-01-06
Edlow, Martin H.
357 24, 357 232, 357 236, 357 2314, H01L 29161, H01L 2978
Patent
active
046350837
ABSTRACT:
A memory device includes a relative lower bandgap energy first semiconductor layer, a relatively higher bandgap energy second semiconductor layer on the first, an alloy source rectifying to the first layer, a well for storing charge and a gate for controlling charge flow between the source and the well. The gate is formed on the second layer, as is a field plate for controlling the storage charge in the well. In one embodiment, a buried channel field effect transistor is combined with the basic memory device, with the charge content of the well controlling current flow between the source and drain of the buried channel FET.
REFERENCES:
patent: 4257057 (1981-03-01), Cheung
patent: 4424525 (1984-01-01), Mimura
patent: 4433343 (1984-02-01), Levine
Edlow Martin H.
Purdue Research Foundation
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