Memory device

Static information storage and retrieval – Powering – Conservation of power

Reexamination Certificate

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Details

C365S154000

Reexamination Certificate

active

07852700

ABSTRACT:
A memory device includes a power supply line, a memory cell, a memory cell power supply node provided between the memory cell and the power supply line, a first voltage generating circuit coupled to the memory cell power supply node for supplying the memory cell power supply node with a first potential lower than a potential of the power supply line for a first period corresponding to at least a part of a writing operation period, and a second voltage generating circuit that is coupled to the memory cell power supply node for supplying the memory cell power supply node with a second potential lower than the potential of the power supply line for a second period corresponding to at least a part of the writing operation period.

REFERENCES:
patent: 2006/0262628 (2006-11-01), Nii et al.
patent: 2008/0055967 (2008-03-01), Houston et al.
patent: 2002-042476 (2002-02-01), None
patent: 2007-004960 (2007-01-01), None
S. Ohbayashi et al, “A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits”, Jun. 15, 2006, Hyogo, Japan.

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