Memory device

Details Memory device Memory device

2007-08-21

2007-08-21

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185240, C365S185180

Reexamination Certificate

active

11016666

ABSTRACT:
A method of stabilizing a memory device comprises trapping a plurality of electric charges in a charge trapping layer of the memory device. The charge trapping layer is positioned between a transistor control gate and a transistor channel region. The method further comprises applying a negative voltage bias to the transistor control gate. In another embodiment, the method further comprises performing a baking process on the memory device. The method further comprises performing a memory operation on the memory device.

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patent: 6847556 (2005-01-01), Cho
Lusky et al., “Electrons Retention Model for Localized Charge in Oxide-Nitride-Oxide (ONO) Dielectric”, IEEE Electron Device Letters, vol. 23, No. 9, pp. 556-558 (Sep. 2002).
Yang et al., “Charge Retention of Scaled SONOS Nonvolatile Memory Devices at Elevated Temperatures”, Solid State Electronics 44 (2000) pp. 949-958.

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