Memory device

Details Memory device Memory device

2006-10-17

2006-10-17

Lam, David (Department: 2827)

Static information storage and retrieval

Floating gate

Particular biasing

C365S185290, C365S185170

Reexamination Certificate

active

07123518

ABSTRACT:
A memory device including a plurality of word lines, a plurality of bit lines, at least four control lines and a plurality of memory cells is provided. The bit lines are disposed in a perpendicular direction of the word lines. Each memory cell is disposed at an intersection of one of the word lines and one of the bit lines, and every four sequential memory cells having a common word line are connected to the four control lines respectively. In addition, in each of the memory cells, the control line thereof is disposed between the bit line thereof and the word line thereof, and is parallel to the bit line thereof, wherein each of the memory cell is provided as a bit.

REFERENCES:
patent: 6163049 (2000-12-01), Bui
patent: 6477088 (2002-11-01), Ogura et al.
patent: 6859397 (2005-02-01), Lutze et al.
patent: 6925007 (2005-08-01), Harari et al.

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