Memory decoder circuit

Details Memory decoder circuit Memory decoder circuit

1984-02-10

1986-12-02

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

Transistors or diodes

365 51, 365 63, G11C 506

Patent

active

046270280

ABSTRACT:
In an NOR decoder for a static random access memory the individual transistor gates (30) are coupled to metallization tracks (31) via polysilicon contact islands (33). The gates of selected transistors are divided into two portions (20a, 20b) disposed on diametrically opposite sides of the corresponding islands (33). This arrangement allows a closer spacing of the tracks (31) than is achieved in conventional layouts.

REFERENCES:
patent: 4145622 (1979-03-01), Hofmann et al.

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