Memory data protection circuit

Details Memory data protection circuit Memory data protection circuit

1997-01-21

1998-10-20

Beausoliel, Jr., Robert W.

G06F 1100

Patent

active

058260072

ABSTRACT:
A memory data protection circuit is provided on a one-chip microcomputer having a CPU, ROM, volatile memory, and nonvolatile memory which together with an input/output control circuit are connected to each other via a first bus line. A security flag storage circuit receives a security flag consisting of a plurality of bits. In one state the security flag cannot be rewritten once it has been written. A security flag monitor circuit reads the security flag and when receiving the power-on reset signal recognizes the flag contents. A bus line control circuit controls the connections of the first bus line, a second bus line connected to the ROM, and a third bus line connected to a test-only memory in response to the security flag monitor circuit When the security flag indicates test mode before shipment, the bus line control circuit controls connections so a shift to the test mode may be possible; when it indicates normal operation mode after shipment, a shift to the test mode may be impossible; and when it indicates test mode after shipment, a shift to the test mode may be possible with the ROM disconnected from the second bus line.

REFERENCES:
patent: 4698750 (1987-10-01), Wilkie et al.
patent: 5014191 (1991-05-01), Padgaonkar et al.
patent: 5293610 (1994-03-01), Schwarz
patent: 5432950 (1995-07-01), Sibigtroth
patent: 5526311 (1996-06-01), Kreifels et al.
patent: 5563832 (1996-10-01), Kagami
patent: 5704039 (1994-07-01), Yishay et al.

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