Static information storage and retrieval – Powering – Data preservation
Patent
1985-12-31
1987-05-26
Popek, Joseph A.
Static information storage and retrieval
Powering
Data preservation
365226, G11C 1300
Patent
active
046690662
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a memory data holding circuit which, in case of power supply interruption, supplies an operating current from a backup power supply to a memory to retain its stored data.
A device using a memory is sometimes provided with a data holding circuit which, in case of power source interruption, supplies an operating current from a backup power supply to the memory, preventing destruction of its stored data.
FIG. 5 illustrates in block form an example of a conventional data holding circuit. Reference numeral 1 indicates a memory such as a C-MOS-RAM or the like, 2 a power supply unit which supplies an operating voltage V.sub.CC to each part of the device and yields a detecting signal a which goes to a "1" in the power-ON state and a "0" in the power-OFF state, 3 a backup power supply, 4 a changeover switch which is connected to the side of a contact A or B depending upon whether the detecting signal a is at the "1" or "0" level, 5 an AND gate and 6 an input terminal for a chip select signal b. Incidentally, the detecting signal a goes to the "1" state a certain elapsed time after the rise of the operating voltage V.sub.CC and goes to the "0" state a certain time before the fall of the operating voltage V.sub.CC. The memory 1 is accessible when the chip select signal b is at the "1" level which is applied via the AND gate 5.
While the operating voltage V.sub.CC is supplied to each part of the device from the power supply unit 2, the detecting signal a is at "1", so the changeover switch 4 will be connected to the contact A side, through which the operating voltage V.sub.CC is provided to the memory 1. Furthermore, since the AND gate 5 is in the ON state in this instance, the chip select signal b will be applied via the AND gate 5 to the memory 1. Moreover, when the power supply is turned OFF, the detecting signal a goes to a "0", so the changeover switch 4 is connected to the contact B side and the backup power supply 3 will provide an operating current to the memory 1, holding its stored contents.
With a view to preventing access to the memory 1 during the power-OFF period, however, the conventional arrangement shown in FIG. 5 is adapted so that the chip select signal b is applied to the memory 1 via the AND gate 5 which is controlled by the detecting signal a. This introduces a defect as follows: That is, if power is disconnected from the device when the chip select signal b is at "1" and data is being written in the memory 1, the AND gate 5 will be turned OFF to discontinue the access to the memory 1 although data is being written therein, so that the contents stored at an address being accessed at that time may sometimes become inidentifiable.
SUMMARY OF THE INVENTION
The present invention is intended to overcome such a defect as mentioned above, and has for its object to ensure holding the stored contents of a memory in case of power disconnection.
The present invention includes a first detecting means for detecting the interruption of power supply and a second detecting means for detecting whether the memory is being accessed or not. Only when the first detecting means detects that the power supply is OFF and the second detecting means detects that the memory is not being accessed, access to the memory is prohibited and an operating current is supplied to the memory from a backup power supply. This ensures that the stored contents of the memory are retained even if the power source is turned OFF when the memory is being accessed.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of an embodiment of the present inventin;
FIG. 2 is a circuit diagram of an example of the arrangement of a control circuit 7 of FIG. 1;
FIG. 3 is a diagram for explaining operations of the circuits depicted in FIGS. 1 and 2;
FIG. 4 is a diagram of the principal part of another embodiment of the present invention; and
FIG. 5 is a block diagram of a prior art example.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 1 illustrates in block form an emb
REFERENCES:
patent: 4388706 (1983-06-01), Butler
patent: 4587640 (1986-05-01), Saitoh
Kagawa Yoshimasa
Nakazono Kazushige
Fanuc Ltd.
Popek Joseph A.
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