Memory data access scheme

Details Memory data access scheme Memory data access scheme

2007-08-14

2007-08-14

Nguyen, Tan T. (Department: 2827)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S238500

Reexamination Certificate

active

11151332

ABSTRACT:
A bitline selection network is composed of a plurality of bitlines and a plurality of global bitlines. The bitlines are grouped into bytes with eight bitlines per byte. The bitlines provide access to memory cells for read and write operations. A bitline is connected to a global bitline through a bitline select transistor. Each of the bitline select transistors is activated one at a time by a bitline select controller. Activation of each bitline select transistor provides a connection to a source line, which in turn connects to a sense amplifier and a write data loading logic block. The sense amplifier and the write data loading logic block are used in read and write operations respectively.

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