Memory controller with synchronous or asynchronous interface

Details Memory controller with synchronous or asynchronous interface Memory controller with synchronous or asynchronous interface

1983-09-19

1986-09-30

Thomas, James D.

Boots, shoes, and leggings

G06F 1300

Patent

active

046150170

ABSTRACT:
A common memory interfacing circuit and method for coupling a memory to either a synchronous bus or an asynchronous bus. Synchronizing means are provided for synchronizing memory request signals with a local clock when the interfacing circuit is coupled to an asynchronous bus. The interface circuit responds to signals from the memory when internal memory operation has been completed and generates an acknowledge signal to send to the requesting bus. To simplify the common interface circuit, a synchronous protocol for information exchange between system components is made similar to an asynchronous protocol.

REFERENCES:
patent: 3848233 (1974-11-01), Lotan et al.
patent: 3993981 (1976-11-01), Cassarino, Jr. et al.
patent: 3999163 (1976-12-01), Levy et al.
patent: 4007448 (1977-02-01), Sergeant et al.
patent: 4151593 (1979-04-01), Jenkins et al.
patent: 4300194 (1981-11-01), Bradley et al.
patent: 4319323 (1982-03-01), Ermolovich et al.
IBM Tech. Discl. Bull., vol. 19, No. 10, "Common I/O and Storage Interface" by W. E. Tutt, Mar. 1977, pp. 3643-3647.

Affiliated with

Also associated with

Rating

Memory controller with synchronous or asynchronous interface does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory controller with synchronous or asynchronous interface, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller with synchronous or asynchronous interface will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-988110