Memory controller with staggered request signal output

Details Memory controller with staggered request signal output Memory controller with staggered request signal output

2008-01-22

2008-01-22

Elms, Richard T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S191000, C365S194000, C365S201000, C365S230080

Reexamination Certificate

active

11252957

ABSTRACT:
A memory controller having a time-staggered request signal output. A first timing signal is generated with a phase offset relative to a first clock signal in accordance with a first programmed value, and a second timing signal is generated with a phase offset relative to the first clock signal in accordance with a second programmed value. An address value is transmitted in response to the first timing signal and a control value is transmitted in response to the second timing signal, the address value and control value constituting portions of a first memory access request.

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