Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2011-06-07
2011-06-07
Dinh, Son (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S193000
Reexamination Certificate
active
07957218
ABSTRACT:
A dual data rate (DDR) memory controller and method are provided. The method includes: receiving a first data strobe at a first terminal from a first memory having a first rank; receiving a first data signal at a second terminal from the first memory having the first rank; calibrating the first data signal with the first data strobe to produce a first calibration value; receiving a second data strobe at the first terminal from a second memory having a second rank; receiving a second data signal at the second terminal from the second memory having the second rank; calibrating the second data signal with the second data strobe to produce a second calibration value; determining a final calibration value using the first and second calibration values; and using the final calibration value to time the first data signal and the second data signal during a read operation of the memories.
REFERENCES:
patent: 6975556 (2005-12-01), Schoenfeld et al.
patent: 7164742 (2007-01-01), McLeod
patent: 7441139 (2008-10-01), Kuwata
patent: 7460418 (2008-12-01), Jung et al.
Clingan, Jr. James L.
Dinh Son
Freescale Semiconductor Inc.
Hill Daniel D.
Nguyen Nam T
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