Memory controller with queue control apparatus

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G06F 1300

Patent

active

043665381

ABSTRACT:
A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the controller to operate in a corresponding number of different modes. The controller includes queue timing and control apparatus which couples to the modules and to the queue circuits for minimizing conflicts between the types of requests and the internal operations required to be performed by the controller.

REFERENCES:
patent: 4001790 (1977-01-01), Barlow
patent: 4050097 (1977-09-01), Miu et al.
patent: 4121286 (1978-10-01), Venton et al.
patent: 4228500 (1980-10-01), Webster

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