Memory controller with programmable timing

Details Memory controller with programmable timing Memory controller with programmable timing

1992-08-31

1995-05-23

Rudolph, Rebecca L.

Boots, shoes, and leggings

364DIG1, 3642702, 395550, G06F 926

Patent

active

054189241

ABSTRACT:
A memory controller for controlling access to a memory includes a circuit for generating memory signals, including address and control signals, for accessing a memory in response to a physical address, and a circuit for programming the timing of the memory signals in response to predetermined timing control information which defines the timing requirements of the memory. The circuit for programming the timing of the memory preferably includes a register for storing timing control bits and selectors responsive to the timing control bits for selecting timing control parameters from a group of predetermined timing control parameters. The circuit for programming the timing preferably further includes a circuit responsive to each timing control parameter and to a selected memory signal for generating a timing control signal. The timing control signal controls the timing of one of the memory signals. The timing parameters can specify the duration of a memory signal or the time delay between a predefined event in one memory signal and a predefined event in another memory signal. The programmable feature permits the memory controller to be utilized with memories having different timing requirements.

REFERENCES:
patent: 4755964 (1988-07-01), Miner
patent: 5097437 (1992-03-01), Larson
patent: 5276856 (1994-01-01), Norsworthy et al.

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