Memory controller with multi-modal reference pad

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C365S189070, C365S189090, C365S189030

Reexamination Certificate

active

08068357

ABSTRACT:
A memory controller operates in two modes to support different types of memory devices. In a first mode, the memory controller distributes a dedicated reference voltage with each of a plurality of signal bundles to a corresponding plurality of memory devices. The reference voltages are conveyed using pads that are alternatively used for e.g. timing-reference signals in a second mode, so the provision for bundle-specific reference voltages need not increase the number of pads on the memory controller.

REFERENCES:
patent: 6310796 (2001-10-01), Song
patent: 6513081 (2003-01-01), Farmwald
patent: 6546343 (2003-04-01), Batra et al.
patent: 6675272 (2004-01-01), Ware et al.
patent: 6707724 (2004-03-01), Kim et al.
patent: 6859067 (2005-02-01), Yamamoto
patent: 6870783 (2005-03-01), Kwak et al.
patent: 7133945 (2006-11-01), Lau
patent: 7162376 (2007-01-01), Oh
patent: 7489153 (2009-02-01), Spirkl
patent: 2005/0240744 (2005-10-01), Shaikh et al.
patent: 2007/0283076 (2007-12-01), Kim et al.
Poulton, John., “Signaling in High Performance Memory Systems”, IEEE Solid State Circuits Conference, slides 1-59 on 30 pages (Feb. 1999).
Micron, “Graphics DDR3 DRAM.” Advance. “256 Mb×32 GDR3 DRAM.” © 2003 Micron Technology, Inc. pp. 1-66.
Janzen, Jeff, “DDR2 Offers New Features and Functionality,” Designline, vol. 12, Issue 2, Micron, 16 pages, Jul. 31, 2003 EN.L.
Samsung, “512Mb E-die DDR3 SDRAM Specification”, Preliminary Specification, Rev. 0.5, Dec. 2006, 55 pages.
Samsung, DDR3 SDRAM Specification. Rev. 0.1, Jan. 2007, Unbuffered DIMM, 59 pages.
Samsung, DDR3 SDRAM Specification; Rev. 0.0, 66 pages, Jan. 2007, DDR3 SDRAM Device Operation.
Micron (Advance), 1Gb DDR3 SDRAM, MT41J256M4—32 Meg×4×8 banks, MT41J128M8—16 Meg×8×8 banks, MT41J64M16—8 Meg×16×8 banks; 2006, 15 pgs.
Micron, DDR2 SDRAM SODIMM, MT16HTF6464H—512MB, MT16HTF12864H—1GB, MT16HTF25664H—2GB, 2004-2005, 22 pgs. Rev. A 1/06 EN.
Samsung, DDR2 SDRAM, Device Operating & Timing Diagram, 44 pgs., May 2007.
Samsungn, 512Mbit GDDR4 SGRAM Revision 1.0 Jun. 2006, 70 pages.
Hynix, Preliminar 240pin DDRS SDRAM Unbuffered DIMMS, Revision 0.02, Feb. 2007, 53 pages.
Lattice Semiconductor Corporation, Differential Signaling, Application Note AN6019. May 2001. 4 pages.
Samsung, 512Mbit GDDR3 SDRAM, Revision 1.5, Jun. 2006. 59 pages.
Dally, William J. and Poulton, John W., Digital Systems Engineering, Publishing page and pp. 314-352, first printed in 1998.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Memory controller with multi-modal reference pad does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Memory controller with multi-modal reference pad, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Memory controller with multi-modal reference pad will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-4284699

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.