Memory controller having bus master for addressing instruction m

Details Memory controller having bus master for addressing instruction m Memory controller having bus master for addressing instruction m

1993-08-02

1996-04-02

Kim, Matthew M.

Boots, shoes, and leggings

39542103, 395450, 395375, 395484, 364DIG1, 3642433, G06F 926, G06F 932, G06F 1206

Patent

active

055048714

ABSTRACT:
Instruction memories and a data memory are connected to a bus master which inputs or outputs an address signal and a data signal. The instruction memories are interleaved and are driven by a predicted address. The predicted address is retained upon accessing the data memory. As long as instruction codes are consecutive and addresses are not changed intentionally, effects of the interleaved arrangement can be shown even where a data area exists in the instruction codes.

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