Memory controller having all DRAM address and control singals pr

Details Memory controller having all DRAM address and control singals pr Memory controller having all DRAM address and control singals pr

1996-03-05

1997-07-29

Ray, Gopal C.

Static information storage and retrieval

Magnetic bubbles

Guide structure

395494, 395881, 365193, 365233, G06F 1202

Patent

active

056528566

ABSTRACT:
A memory controller which makes maximum use of any processor pipelining and runs a large number of cycles concurrently. The memory controller takes advantage of different speed memory devices by operating each memory device at optimal speed. The functions are performed by a plurality of simple, interdependent state machines, each responsible for one small portion of the overall operation. As each state machine has completed its function, it notifies a related state machine that it can now proceed and thereafter waits for its next start or proceed indication. The next state machine operates in a similar fashion. The state machines responsible for the earlier portions of a cycle have started their tasks on the next cycle before the state machines responsible for the later portions of the cycle have completed their tasks. The memory controller is logically organized as three main blocks, a front end block, a memory block and a host block, each being responsible for interactions with its related bus and components and interacting with the various other blocks for handshaking. The memory system includes a single chip comprising a plurality of flip-flops which provides all of the address and control signals to a memory device so that a clock cycle can be saved because of reduced skew of the signals. These flip-flops are synchronously clocked by a common clock and provide the final output of the address and control signals for the DRAM devices.

REFERENCES:
patent: 4694197 (1987-09-01), Sprague
patent: 5327390 (1994-07-01), Takasugi
C. H. Chan, et al., A CMOS Multi-Mode Data Acquisition System Implemented Using a Workstation Based VLSI Design Environment, IEEE, Electronicom '85, Oct. 6-11, 1985, pp. 28-31.
IBM Technical Diclosure Bull., Direct, Asynchronous and Synchronous Storage Card, vol. 29, No. 4, Sep. 1986, pp. 1452-1456.

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